Packaged integrated device

A memory module, comprising:

• a module substrate;
• memory devices disposed on the module substrate;
• a packaged integrated device disposed on the module substrate, the packaged integrated device having a package substrate having a package substrate surface that is substantially rectangular, the package substrate surface having a first edge and a second edge, the first edge and the second edge defining a package centerline that is substantially parallel to the first edge and the second edge and substantially equidistant between the first edge and the second edge, the package substrate also having a first plurality of connection conductors comprising solder balls and a second plurality of connection conductors comprising solder balls;
• a memory buffer integrated circuit die disposed on the package substrate surface and having a first plurality of die connection conductors and a second plurality of die connection conductors, the first plurality of die connection conductors connected to the first plurality of connection conductors via a first plurality of signal conductors, the second plurality of die connections connected to the second plurality of connection conductors via a second plurality of signal conductors, the memory buffer integrated circuit configured to receive at least a first plurality of command/address signals via the first plurality of die connection conductors and to transmit a second plurality of command/address signals to the memory devices via the second plurality of die connections;
• the first plurality of connection conductors disposed between the package centerline and the first edge, the second plurality of connection conductors disposed between the first plurality of connection conductors and the second edge;
• and
• the memory buffer integrated circuit disposed such that a first average distance from the memory buffer integrated circuit die to the first plurality of connection conductors is less than a second average distance from the memory buffer integrated circuit die to the second plurality of connection conductors.

A memory module, comprising:

• a module substrate;
• memory devices disposed on the module substrate;
• and
• a packaged integrated device disposed on the module substrate and having a memory buffer integrated circuit, the packaged integrated device having a package substrate having a package substrate surface, the package substrate comprising host command/address signal balls connected to host command/address signal conductors of the memory module, and memory device command/address signal balls connected to memory device command/address signal conductors of the memory module, the memory buffer integrated circuit mounted to the package substrate and offset from a center axis of the package substrate, the host command/address signal conductors being connected to host die connections that couple to host command/address interface circuits on the memory buffer integrated circuit, the memory device command/address signal conductors being connected to memory device die connections that coupled to command/address interface circuits on the memory buffer integrated circuit, a majority of lengths of the host command/address signal conductors being less than a majority of lengths of the memory device command/address signal conductors.

A memory module, comprising:

• a module substrate;
• memory devices disposed on the module substrate;
• and
• a ball grid array (BGA) package disposed on the module substrate and comprising a package substrate comprising host command/address signal balls connected to host command/address signal conductors, and memory device command/address signal balls connected to memory device command/address signal conductors, the host command/address signal balls and the memory device command/address signal balls configured to electrically connect the BGA package to the module substrate, the BGA package including a memory buffer integrated circuit, the host command/address signal balls connected to host command/address signal interface circuits of the memory buffer integrated circuit via the host command/address signal conductors, the memory device command/address signal balls connected to memory device command/address signal interface circuits of the memory buffer integrated circuit via the memory device command/address signal conductors, the memory buffer integrated circuit mounted to the package substrate such that an average distance from host command/address signal interface circuits to the host command/address signal balls is less than a second average distance from the memory device command/address signal interface circuits to the memory device command/address signal balls.