Semiconductor package

A semiconductor package comprising:

• a package substrate including a redistribution layer including first pads and second pads on an upper surface of the package substrate and a solder mask layer having an opening entirely exposing the first pads and exposing at least portion of each of the second pads;
• a semiconductor structure on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer;
• and
• connection bumps connecting the connection pads to the first pads,
• wherein the second pads are respectively disposed on both sides of a group of the first pads in a first direction;
• the first pads and the second pads are arranged at a first pitch, and
• the connection bumps are spaced apart from the solder mask layer in the first direction by a distance of about 30% or more of the first pitch.

A semiconductor package comprising:

• a package substrate including a redistribution layer including first pads and second pads on an upper surface of the package substrate and a solder mask layer having an opening entirely exposing the first pads and exposing at least portion of each of the second pads;
• a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer;
• connection bumps connecting the connection pads to the first pads;
• and
• a non-conductive film layer between the semiconductor chip and the package substrate, the non-conductive film layer surrounding the connection bumps,
• wherein the second pads are respectively disposed on both sides of a group of the first pads in a first direction, and
• upper surfaces and side surfaces of the second pads are entirely covered by the solder mask layer and the non-conductive film layer.