Packaging architecture with rounded traces for on-package high-speed interconnects

A package substrate, comprising:

• a first layer comprising a first conductive plane;
• a second layer comprising a dielectric material;
• a third layer comprising a second conductive plane and a third conductive plane, the second conductive plane and the third conductive plane separated from a conductive trace by the dielectric material, the second layer between the first layer and the third layer;
• a fourth layer comprising the dielectric material;
• and
• a fifth layer comprising a fourth conductive plane,
• wherein:
• the second layer is between the first layer and the third layer,
• the fourth layer is between the third layer and the fifth layer, and
• the conductive trace has rounded corners.

A method, comprising:

• providing a layer of a dielectric material;
• depositing a seed layer comprising metal on the dielectric material;
• depositing photoresist on the seed layer;
• selectively removing the photoresist to form trenches in desired regions;
• and
• depositing conductive material in the trenches,
• wherein, after the photoresist is selectively removed and before the conductive material is deposited:
• at least one trench has a first width,
• the at least one trench has parallel walls of the photoresist in a first portion and concave fillets of the photoresist in a second portion,
• the second portion is between the first portion and the seed layer,
• the seed layer is exposed in a gap of a second width in the photoresist between the concave fillets,
• the second width is smaller than the first width.