Methods for producing a 3d semiconductor device and structure with memory cells and multiple metal layers

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming a first metal layer on top of said first level;
• forming a second metal layer on top of said first metal layer;
• forming at least one second level disposed on top of or above said second metal layer;
• performing a first lithography step on said second level;
• forming at least one third level disposed on top of or above said at least one second level;
• performing additional processing steps to form a plurality of first memory cells within said at least one second level;
• performing said additional processing steps to form a plurality of second memory cells within said at least one third level,
• wherein said additional processing steps comprise deposition processes and etch processes,
• wherein each of said plurality of first memory cells comprises at least one second transistor,
• wherein each of said plurality of second memory cells comprises at least one third transistor;
• forming a third metal layer disposed on top of or above said at least one third level;
• and
• forming a through layer via (TLV) connecting said third metal layer to said second metal layer,
• wherein said through layer via comprises an average diameter of less than 400 nm;
• and
• forming at least four independent memory arrays,
• wherein said at least four independent memory arrays comprise portions of said plurality of first memory cells and/or portions of said plurality of second memory cells.

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming a first metal layer on top of said first level;
• forming a second metal layer on top of said first metal layer;
• forming at least one second level disposed on top of or above said second metal layer;
• performing a first lithography step on said second level;
• forming at least one third level disposed on top of or above said at least one second level;
• performing additional processing steps to form a plurality of first memory cells within said at least one second level;
• performing said additional processing steps to form a plurality of second memory cells within said at least one third level,
• wherein said additional processing steps comprise deposition processes and etch processes,
• wherein each of said plurality of first memory cells comprises at least one second transistor,
• wherein each of said plurality of second memory cells comprises at least one third transistor, and
• wherein said first metal layer has an average thickness which is 50% greater than an average thickness of said second metal layer;
• and
• forming at least four independent memory arrays,
• wherein said at least four independent memory arrays comprise portions of said plurality of first memory cells and/or portions of said plurality of second memory cells.