Memory device, memory system, and operating method thereof

A memory device, comprising:

• a memory cell array including memory cells;
• and
• peripheral circuitry coupled to the memory cell array through word lines and configured to
• apply an N-th programming pulse to the memory cells each with a target programming state being an i-th programming state, wherein i and N are positive integers,
• perform a first sub-verification and an M-th second sub-verification corresponding to the i-th programming state on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively, wherein M is a positive integer, the first sub-result indicates whether a threshold voltage of each of the memory cells is less than a preset voltage, the M-th second sub-result indicates whether the threshold voltage of each of the memory cells is less than a target threshold voltage of the i-th programming state, and wherein the target threshold voltage is greater than the preset voltage,
• determine a first subset of the memory cells to be programmed with an (N+1)-th programming pulse, based on the M-th second sub-result, wherein a voltage difference between the (N+1)-th programming pulse and the N-th programming pulse is greater than or equal to a voltage difference between the target threshold voltage and the preset voltage, and
• apply the (N+1)-th programming pulse to the word line, wherein the memory cells are determined to be successfully programmed to the i-th programming state after applying the (N+1)-th programming pulse to the word line, based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.

A memory system, comprising:

• a memory device comprising
• a memory cell array including memory cells, and
• peripheral circuitry coupled to the memory cell array through word lines and configured to
• apply an N-th programming pulse to a word line coupled to the memory cells each with a target programming state being an i-th programming state, wherein i and N are positive integers,
• perform a first sub-verification and an M-th second sub-verification corresponding to the i-th programming state on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively, wherein M is a positive integer, the first sub-result indicates whether a threshold voltage of each of the memory cells is less than a preset voltage, the M-th second sub-result indicates whether the threshold voltage of each of the memory cells is less than a target threshold voltage of the i-th programming state, and wherein the target threshold voltage is greater than the preset voltage,
• determine a first subset of the memory cells to be programmed with an (N+1)-th programming pulse, based on the M-th second sub-result, wherein a voltage difference between the (N+1)-th programming pulse and the N-th programming pulse is greater than or equal to a voltage difference between the target threshold voltage and the preset voltage, and
• apply the (N+1)-th programming pulse to the word line, wherein the memory cells are determined to be successfully programmed to the i-th programming state after applying the (N+1) programming pulse to the word line, based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value;
• and
• a memory controller coupled to the memory device and configured to control the memory device.