Memory system having semiconductor memory device that performs verify operations using various verify voltages

A method of controlling a semiconductor memory device that includes a plurality of memory cells and a word line, the plurality of memory cells corresponding to a first page, the plurality of memory cells comprising first, second, third, and fourth memory cells, the word line being electrically connected to gates of the first, second, third, and fourth memory cells, the method comprising:

• receiving a first write command;
• in response to the received first write command, executing a first program operation on the first page and a first verify operation on the first page using a first verify condition;
• receiving a second write command;
• and
• in response to the received second write command, executing
• a pre-verify operation on a first subset of the first page using a second verify condition, the first subset corresponding to the first and second memory cells, a second program operation on the first subset of the first page, and a second verify operation on the first subset of the first page using the second verify condition when the received second write command corresponds to the first subset of the first page, and
• a pre-verify operation on a second subset of the first page using a third verify condition, the second subset corresponding to the third and fourth memory cells, the second program operation on the second subset of the first page, and a third verify operation on the second subset of the first page using the third verify condition when the received second write command corresponds to the second subset of the first page.