Reliability improvement through delay between multi-stage programming steps in non-volatile memory structures

A memory controller, comprising:

• a communication pathway configured to couple to a memory block of a non-volatile memory structure, wherein the memory block comprises a plurality of NAND-type memory cells;
• and
• the memory controller is configured to:
• initiate a programming operation with respect to the memory block;
• apply a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage;
• and
• between the first programming stage and the second programming stage, apply a time delay according to a pre-determined amount of time, wherein the pre-determined amount of time is defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell as a result of the first programming stage.

A non-volatile memory system, comprising:

• a memory block comprising a population of NAND-type memory cells;
• and
• a memory controller coupled to the memory array and:
• initiating a programming operation with respect to the memory block;
• applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage;
• and
• between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time, wherein the pre-determined amount of time is defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell as a result of the first programming stage.