Memory apparatus using semiconductor devices

A memory apparatus using semiconductor devices, comprising:

• a page including a plurality of memory cells arranged in a column on a substrate,
• wherein:
• each memory cell included in the page has
• a semiconductor base material provided on the substrate in a manner standing in an upright position along a vertical direction or extending in a horizontal direction with respect to the substrate,
• a first impurity region and a second impurity region at opposite ends of the semiconductor base material,
• a gate insulating layer in contact with a side face of the semiconductor base material between the first impurity region and the second impurity region,
• a first gate conductor layer partially or entirely covering the gate insulating layer, and
• a second gate conductor layer adjacent to the first gate conductor layer and in contact with a side face of the gate insulating layer,
• in each of the individual memory cells,
• each of voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region is controlled to allow holes generated through an impact ionization phenomenon or using a gate induced drain leakage current to be retained in the semiconductor base material, and
• during a page write operation, a voltage of the semiconductor base material is set to a first data holding voltage that is higher than one or both of a voltage of the first impurity region and a voltage of the second impurity region, and
• in all of the individual memory cells forming the page, during a page erase operation,
• the voltage of the semiconductor base material is controlled to a voltage higher than the first data holding voltage through one or both of first capacitive coupling between the first gate conductor layer and the semiconductor base material and second capacitive coupling between the second gate conductor layer and the semiconductor base material, and until the voltage of the semiconductor base material has become higher than one or both of the voltage of the first impurity region and the voltage of the second impurity region, the holes are removed from the semiconductor base material through one or both of the first impurity region and the second impurity region, and
• the voltage of the semiconductor base material is set to a second data holding voltage lower than the first data holding voltage through the first capacitive coupling and the second capacitive coupling.