Low-power static random access memory
AssigneeUntether Ai Corporation
InventorsKatsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN, Joseph Francis ROHLMAN
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Abstract
A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
Claims15
A static random-access memory comprising:
- a word line circuit for generating a word line signal on a word line;
- a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell comprises:
- a first inverter;
- a second inverter, the first inverter and the second inverter configured to operate at a power supply voltage (Vdd);
- a first n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a first output of the first inverter to the first bitline;
- a second n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a second output of the second inverter to the second bitline;
- and
- a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
Dependencies are inferred from the claim text.