Method and apparatus for recovering regular access performance in fine-grained dram

A data processing system, comprising:

• a plurality of processing units;
• a data fabric coupled to the plurality of processing units;
• a memory controller coupled to the data fabric for fulfilling memory access requests from the processing units;
• and
• a high-bandwidth memory (HBM) including at least one fine-grained dynamic random-access memory (DRAM) in communication with the memory controller, each of the at least one fine-grained DRAM comprising:
• a first memory bank including a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry;
• a second memory bank;
• and
• a dual-mode I/O circuit coupled to the I/O circuitry of each grain in the first memory bank, the dual-mode I/O circuit operating in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

A high-bandwidth memory (HBM) comprising:

• a plurality of fine-grained dynamic random-access memories (DRAMs) each comprising:
• a first memory bank including a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry;
• a second memory bank;
• and
• a dual-mode I/O circuit coupled to the I/O circuitry of each grain in the first memory bank, the dual-mode I/O circuit operating in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.