Sense amplifier circuit, memory device including the same and sensing method of memory device

A memory device comprising:

• a first memory cell;
• a first bitline electrically connected to the first memory cell;
• and
• a sense amplifier circuit comprising:
• a first node;
• a second node;
• a first transistor electrically connected between the first bitline and the first node;
• a first inverter comprising an input terminal that is electrically connected to the first node;
• and
• a second inverter comprising an input terminal that is electrically connected to the second node,
• wherein the sense amplifier circuit is configured to perform operations comprising:
• during a first time period, transferring a first voltage to the first node and the second node while the first transistor is turned on;
• during a second time period after the first time period, transferring a second voltage higher than the first voltage to the first node and the second node while the first transistor is turned off;
• during a third time period after the second time period, connecting the first bitline and the first node through the first transistor;
• during a fourth time period after the third time period, connecting an output terminal of the first inverter and the input terminal of the second inverter;
• and
• during a fifth time period after the fourth time period, connecting the first inverter and the second inverter as a cross-coupled latch while the first transistor is turned off.

A sensing method of a memory device, comprising:

• precharging a bitline with a first voltage;
• precharging a first node with a second voltage higher than the first voltage, and sharing charges between a memory cell and the bitline;
• transferring the charges between the first node and the bitline;
• connecting a first inverter comprising an input terminal that is electrically connected to the first node with a second inverter comprising an input terminal that is electrically connected to a second node as a single-ended amplifier;
• and
• connecting the first inverter and the second inverter as a cross-coupled latch, and sensing data of the memory cell based on a voltage difference between the first node and the second node.