Semiconductor memory device and memory system including the same

A semiconductor memory device comprising:

• a memory cell array comprising a plurality of memory cell rows, wherein each memory cell row of the plurality of memory cell rows comprises a plurality of memory cells;
• a row decoder configured to enable a first word-line connected to a target memory cell row from among the plurality of memory cell rows, based on a row address accompanied by a write command received from an external memory controller;
• and
• a column decoder configured to:
• access first memory cells in the target memory cell row using first bit-lines, based on a column address;
• perform a first write operation to store data in the first memory cells using a first power supply voltage until a precharge command is applied to the semiconductor memory device;
• and
• perform a second write operation to store the data in the first memory cells using a second power supply voltage from a first time point at which that the precharge command is applied to the semiconductor memory device until a second time point at which the first word-line is disabled,
• wherein a voltage level of the second power supply voltage is greater than a voltage level of the first power supply voltage.

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device,
• wherein the semiconductor memory device comprises:
• a memory cell array comprising a plurality of memory cell rows, wherein each memory cell row of the plurality of memory cell rows comprises a plurality of memory cells;
• a row hammer management circuit configured to:
• count a number of accesses to the each memory cell row based on an active command received from an external memory controller and store the counted number in at least one count cell in the each memory cell row as count data, and
• based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the at least one count cell in a target memory cell row from among the plurality of memory cell rows, to update the count data, and to store the updated count data in the at least one count cell in the target memory cell row;
• and
• a column decoder configured to:
• access a first memory cell from among the plurality of memory cells using a first bit-line, based on a column address;
• and
• store data in the first memory cell using a first power supply voltage or perform an internal write operation to store the count data in the first memory cell using a second power supply voltage during an internal write time interval smaller than a reference write time interval,
• wherein a voltage level of the second power supply voltage is greater than a voltage level of the first power supply voltage.