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US 2023/0420032 A1Published application
Apparatuses and methods for input receiver circuits and receiver masks for same
AssigneeMicron Technology, Inc.
InventorsDean D. Gans, John D. Porter
Life of this patent
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Abstract
Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.
Claims21
(canceled)
A memory device comprising:
- a memory array;
- an input/output (IO) circuit configured to provide data to the memory array, the IO circuit comprising a data input receiver configured to capture an input data signal that is based at least in part on a predefined receiver mask, wherein the receiver mask has a first timing parameter associated with a first voltage level and further has a second timing parameter associated with a second voltage level, wherein the second timing parameter is greater than the first timing parameter;
- and
- an internal latch circuit, wherein a pulse of the input data signal is center aligned to a strobe at the internal latch circuit.
1 more element
A method, comprising:
- receiving, at a data input receiver of a memory device, an input data signal;
- latching, at an internal latch circuit of the memory device, a pulse of the input data signal with a time-variant voltage characteristic that is based at least in part on a receiver mask, wherein the receiver mask is a hexagonal mask shape, wherein the pulse is center aligned to a strobe at the internal latch circuit of the memory device;
- and
- writing data corresponding to the pulse to a memory array of the memory device.
1 more element
An apparatus comprising:
- a data input circuit of a memory device configured to receiving a data input signal, wherein the data input signal comprises a pulse defined, at least in part, by a first timing parameter indicating a length of time between intersections of the pulse with a reference voltage, a first voltage parameter indicating a peak-to-peak voltage, and second voltage parameter indicating an upper voltage and a lower voltage, wherein the second voltage parameter further corresponds to a voltage parameter of a receiver mask;
- and
- an internal latch circuit, wherein the pulse is center aligned to a strobe at the internal latch circuit.
Dependencies are inferred from the claim text.