Asynchronous signal to command timing calibration for testing accuracy
AssigneeMicron Technology, Inc.
InventorsYoshinori Fujiwara, Kevin G. Werhane, Jason M. Johnson, Daniel S. Miller
Life of this patent
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Abstract
A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
Claims20
A delay circuit, comprising:
- one or more delay elements disposed on one or more memory chips of a memory device, wherein each of the one or more delay elements is configured to generate a respective time delay for a reference signal transmitted from a command decoder of the memory device to the respective delay element of the one or more delay elements,
- and wherein the delay circuit is configured to generate one or more calibrated reference signals based on a command signal received at the command decoder by adjusting a time delay between the reference signal and the command signal at the command decoder.
A method, comprising:
- receiving a reference signal at each of one or more delay elements disposed in a memory device, wherein the reference signal has a first time delay with a command signal at a command decoder of the memory device;
- generating a respective time delay for the reference signal received at each of the one or more delay elements based on the command signal received at each of the one or more delay elements;
- generating a respective status value for each of the one or more delay elements based on the respective time delay generated for the reference signal received at each of the one or more delay elements;
- generating a status signal, via a status circuit, based on at least two of the status values for the one or more delay elements;
- in response to the status signal having a first value, adjusting the value of the first time delay and repeating the generating of the status signal by using the adjusted value of the first time delay;
- and
- in response to the status signal having a second value, recording the first time delay.
A circuit comprising:
- A delay chain, disposed on a memory chip, comprising at least two delay elements, wherein the delay chain is configured to generate a particular time delay for a reference signal transmitted from a command decoder to the delay chain;
- and
- a status circuit configured to:
- receive a first status value from a first delay element of the delay chain disposed on the memory chip, wherein the first status value is associated with a first time delay generated for the reference signal by the first delay element;
- receive a second status value from a last delay element of the delay chain disposed on the memory chip, and wherein the second status value is associated with a second time delay generated for the reference signal by the last delay element;
- and
- generate a status signal based on the first status value and the second status value.
Dependencies are inferred from the claim text.