Channel routing for simultaneous switching outputs
AssigneesATI Technologies ULC, Advanced Micro Devices, Inc.
InventorsXuan Chen, Chih-Hua Hsu, Pradeep Jayaraman, Abdussalam Aburwein
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AssigneesATI Technologies ULC, Advanced Micro Devices, Inc.
InventorsXuan Chen, Chih-Hua Hsu, Pradeep Jayaraman, Abdussalam Aburwein
Estimating the term…
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
An integrated circuit having a DDR memory controller, comprising:
An integrated circuit, comprising:
A method of making an integrated circuit having a DDR memory controller and a first DDR memory physical interface circuit on a semiconductor die, comprising:
Dependencies are inferred from the claim text.