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US 2023/0420012 A1Published application
Memory device and zq calibration method
AssigneeChangxin Memory Technologies, Inc.
InventorKai TIAN
Life of this patent
Estimating the term…
Abstract
A memory device includes: two calibration resistor interfaces connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second master chip, and second slave chips, which are commonly connected to the ZQ calibration resistor; in a command mode, a first signal receiver is used to receive a ZQ calibration command, a second signal receiver is used to receive and delay the ZQ calibration command, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and after the calibration is completed, the first slave chips and the second slave chips send a ZQ flag signal through second transmission terminals.
Claims17
A memory device, comprising:
- two calibration resistor interfaces, the two calibration resistor interfaces being connected to a same ZQ calibration resistor;
- and
- a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips, which are commonly connected to the ZQ calibration resistor;
- wherein the first master chip, the first slave chips, the second master chip, and the second slave chips are provided with first transmission terminals and second transmission terminals, and the first transmission terminals and the second transmission terminals are used to transmit a ZQ flag signal;
- and
- wherein a second transmission terminal of the first master chip is connected to a first transmission terminal of a first slave chip of a first stage, a second transmission terminal of a first slave chip of each stage is connected to a first transmission terminal of a first slave chip of a next stage, a second transmission terminal of a second master chip is connected to a first transmission terminal of a second slave chip of a first stage, and a second transmission terminal of a second slave chip of each stage is connected to a first transmission terminal of a second slave chip of a next stage;
- the first master chip is provided with a first signal receiver, the second master chip is provided with a second signal receiver, and the first slave chips and the second slave chips are provided with third signal receivers;
- in a command mode, the first signal receiver is used to receive, through a ZQ signal terminal, a ZQ calibration command provided by a memory, the second signal receiver is used to receive and delay the ZQ calibration command by a ZQ signal terminal, the first master chip and the second master chip start to calibrate based on the ZQ calibration command, and the first master chip and the second master chip send the ZQ flag signal by the second transmission terminals after the calibration is completed, the ZQ flag signal indicating that a current chip has been calibrated with the calibration resistor;
- and
- the third signal receiver is used to receive the ZQ flag signal by the first transmission terminal, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and the first slave chips and the second slave chips send the ZQ flag signal by the second transmission terminals after the calibration is completed until all the first or second slave chips have been calibrated.
7 more elements
A ZQ calibration method, performed by a memory device, comprising:
- obtaining, in a command mode, a ZQ calibration command externally applied to the memory device;
- in response to the ZQ calibration command, performing a first calibration operation on a first master chip;
- after the first calibration operation is completed, transmitting a ZQ flag signal to a first slave chip of a first stage, and at a same time, performing a second calibration operation on the first master chip;
- in response to the ZQ flag signal, performing the first calibration operation on the first slave chip of the first stage;
- after the first calibration operation on the first slave chip of the first stage is completed, transmitting the ZQ flag signal to a first slave chip of a next stage, and at a same time, performing the second calibration operation on the first slave chip of the first stage, until the first calibration operation of a first slave chip of a last stage is completed;
- completing the second calibration operation on the first slave chip of the last stage;
- in response to a delayed ZQ calibration command, performing a first calibration operation on a second master chip;
- after the first calibration operation is completed, transmitting a ZQ flag signal to a second slave chip of a first stage, and at a same time, performing a second calibration operation on the second master chip;
- in response to the ZQ flag signal, performing the first calibration operation on the second slave chip of the first stage;
- after the first calibration operation on the second slave chip of the first stage is completed, transmitting the ZQ flag signal to a second slave chip of a next stage, and at a same time, performing the second calibration operation on the second slave chip of the first stage, until the first calibration operation of a second slave chip of a last stage is completed;
- completing the second calibration operation on the second slave chip of the last stage.
8 more elements
Dependencies are inferred from the claim text.