Smart feedback design for verification

Abstract

Techniques for implementing a smart feedback design for verification that reduce production and verification time by enabling a verification system to perform piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed. Circuit nodes in an emulation model are selected and smart feedback is provided to the nodes in response to signals detected at the nodes such that behavior of unavailable or unverified components to be located at the nodes can be simulated. Smart feedback can be provided to the node to enable verification of the emulation model without having to wait for the unverified or unavailable components to be provided or verified. A request for manufacture may be generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

Dependencies are inferred from the claim text.