Security subsystem for remote attestation

An integrated circuit device, comprising:

• a system interconnect;
• a set of memories coupled to the system interconnect, each of the set of memories having an address write channel at which write addresses associated with memory write operations can be extracted;
• a set of write bitmaps that are respectively associated with the set of memories, wherein each of the set of write bitmaps comprises:
• a bitmap that tracks the write addresses of detected memory write operations to a corresponding memory of the set of memories;
• and
• logic for extracting the write addresses associated with the memory write operations from the address write channel for the corresponding memory and modifying the bitmap based on the write addresses;
• and
• a security subsystem coupled to the system interconnect, wherein the security subsystem is configured to:
• receive an attestation request from a requester;
• send one or more address ranges of interest to the set of write bitmaps;
• obtain a bitmap status from one of the set of write bitmaps indicating that a write address within the one or more address ranges of interest was detected;
• compute a signature based at least in part on the bitmap status;
• and
• return the signature to a requester.