Memory controller with pseudo-channel support
AssigneeAdvanced Micro Devices, Inc.
InventorsHideki Kanayama, YuBin Yao
Life of this patent
Estimating the term…
Abstract
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.
Claims20
A data processor for accessing a memory having a first pseudo channel and a second pseudo channel, comprising:
- at least one memory accessing agent for generating a memory access request;
- a memory controller for providing memory commands to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit;
- and
- a data fabric for converting said memory access request into said normalized request selectively for the first pseudo channel and the second pseudo channel.
A memory controller for providing memory commands to a physical interface circuit for a memory having a first pseudo channel and a second pseudo channel, comprising:
- a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, each comprising:
- a front-end interface circuit for converting normalized addresses into decoded addresses of decoded memory access requests;
- a command queue coupled to said front-end interface circuit for storing said decoded memory access requests;
- and
- an arbiter for selecting among said decoded memory access requests from said command queue according to predetermined criteria and providing selected memory access requests to an output thereof.
A method for a data processor to provide commands to a memory that has a first pseudo channel and a second pseudo channel, comprising:
- generating memory access requests;
- routing said memory access requests selectively between upstream ports and downstream ports of a data fabric, and memory access responses selectively between said downstream ports and said upstream ports of said data fabric;
- decoding said memory access requests in said data fabric according to one of a plurality of pseudo channels including a first pseudo channel and a second pseudo channel;
- processing first memory access requests of said first pseudo channel in a first decoding and command arbitration circuit;
- and
- processing second memory access requests of said second pseudo channel in a second decoding and command arbitration circuit independent of said first decoding and command arbitration circuit.
Dependencies are inferred from the claim text.