Method and System for Accessing A Nonvolatile Memory via SPI Ports
AssigneeGOWIN Semiconductor Corporation
InventorJinghui Zhu
Life of this patent
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Abstract
A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.
Claims20
An apparatus for digital data processing containing a field-programmable gate array (“FPGA”) able to perform user-defined logic functions, comprising:
- a processor having a serial peripheral interface (“SPI”) port and capable of processing information based on executable instructions;
- a flash memory having a flash SPI port and configured to store configuration data persistently;
- and
- an FPGA containing a first SPI port coupling to the flash SPI port of the flash memory and a second SPI port coupling to the SPI port of the processor and configured to selectively facilitate a direct SPI connection between the processor and the flash memory for SPI data transmissions.
A method of providing a memory access between a processor and a memory facilitated by a field-programmable gate array (“FPGA”), the method comprising:
- identifying a serial peripheral interface (“SPI”) port of a processor capable of processing information in accordance with executable instructions;
- coupling the SPI port of the processor to a first SPI port of FPGA via a first SPI connection;
- connecting a second port of FPGA to an SPI port of a memory via a second SPI connection;
- and
- providing a direct SPI connection between the SPI port of processor and the SPI port of memory in response to a memory access command.
An apparatus of providing a memory access between a processor and a memory facilitated by a field-programmable gate array (“FPGA”), comprising:
- means for identifying a serial peripheral interface (“SPI”) port of a processor capable of processing information in accordance with executable instructions;
- means for coupling the SPI port of the processor to a first SPI port of FPGA via a first SPI connection;
- means for connecting a second port of FPGA to an SPI port of a memory via a second SPI connection;
- and
- means for providing a direct SPI connection between the SPI port of processor and the SPI port of memory in response to a memory access command.
Dependencies are inferred from the claim text.