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US 2023/0418764 A1Published application
Tracking streaming engine vector predicates to control processor execution
AssigneeTexas Instruments Incorporated
InventorsDuc Quang Bui, Joseph Raymond Michael Zbiciak
Life of this patent
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Abstract
In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
Claims20
A device comprising:
- a processor core;
- and
- a memory circuit coupled to the processor core and configured to couple to a memory, wherein the processor core is configured to:
- provide a stream instruction to the memory circuit configured to cause the memory circuit to:
- retrieve a set of data elements from the memory;
- generate a vector that includes the set of data elements and a set of invalid elements;
- and
- generate a set of validity indicators associated with the vector;
- receive the vector and the set of validity indicators;
- and
- perform a loop by:
- performing an operation on a first data element of the vector based on a first validity indicator of the set of validity indicators specifying that the first data element is valid;
- refraining from performing the operation on a second data element of the vector based on a second validity indicator of the set of validity indicators specifying that the second data element is invalid;
- and
- exiting the loop based on the set of validity indicators specifying that a predetermined amount of the vector is invalid.
12 more elements
A method comprising:
- providing, by a processor, a stream instruction to a memory circuit configured to cause the memory circuit to:
- retrieve a set of data elements from a memory;
- generate a vector that includes the set of data elements and a set of invalid elements;
- and
- generate a set of validity indicators associated with the vector;
- receiving, by the processor, the vector and the set of validity indicators;
- and
- performing a loop, by the processor by:
- performing an operation on a first data element of the vector based on a first validity indicator of the set of validity indicators specifying that the first data element is valid;
- refraining from performing the operation on a second data element of the vector based on a second validity indicator of the set of validity indicators specifying that the second data element is invalid;
- and
- exiting the loop based on the set of validity indicators specifying that an amount of the vector is invalid.
9 more elements
A device comprising:
- a processor core;
- and
- a memory circuit coupled to the processor core and that includes:
- a memory interface configured to couple to a memory;
- a head register;
- and
- a validity register;
- wherein:
- the processor core is configured to provide a stream instruction;
- the memory circuit is configured to, based on the stream instruction:
- retrieve, via the memory interface, a set of data elements from the memory;
- generate a vector that includes the set of data elements and a set of invalid elements;
- and
- store a subset of the vector in the head register;
- generate a set of validity indicators associated with the vector;
- and
- store a subset of the set of validity indicators in the validity register;
- and
- the processor core is configured to:
- receive the vector and the set of validity indicators;
- and
- perform a loop by:
- performing an operation on a first data element of the vector based on a first validity indicator of the set of validity indicators specifying that the first data element is valid;
- refraining from performing the operation on a second data element of the vector based on a second validity indicator of the set of validity indicators specifying that the second data element is invalid;
- and
- exiting the loop based on the set of validity indicators specifying that an amount of the vector is invalid.
23 more elements
Dependencies are inferred from the claim text.