Slot/sub-slot prefetch architecture for multiple memory requestors

A system comprising:

• multiple processor cores, each including a data cache of a first type;
• multiple data caches, each of a second type, respectively coupled to the multiple processor cores, each of the multiple data caches of the second type including a prefetch unit;
• and
• a shared memory directly coupled to each of the multiple data caches of the second type;
• wherein a first prefetch unit of a first data cache of the second type of the multiple data caches of the second type is configured to supply prefetch data from a selected slot thereof in response to a data request from the corresponding processor core coupled thereto, in which the supplied prefetch data is from one of two sub-slots of the selected slot when the data request corresponds to the data cache of the first type in the corresponding processor core, and in which the supplied prefetch data is from both of the two sub-slots of the selected slot when the data request corresponds to the first data cache of the second type.

A memory controller comprising:

• a first memory interface configured to provide a protocol to process memory requests from a first type of memory;
• a second memory interface coupled to the first memory interface, the second memory interface configured to provide a protocol to process memory requests from a second type of memory;
• and
• a multi-stream prefetch unit coupled to the first and second memory interfaces, the multi-stream prefetch unit including:
• a prefetch unit, and
• a selector configured to selectively enable the prefetch unit to prefetch data in response to a memory request based on which of the first or second memory interfaces the memory request was received through.