Selective provisioning of supplementary micro-operation cache resources

A method at a processor, the method comprising:

• monitoring a performance of multiple caches of the processor, the multiple caches comprising a first cache and a second cache, wherein the first cache is coupled to receive micro-operations from an instruction decoder, and wherein the second cache is coupled to receive data, or to receive instructions to be provided to the instruction decoder;
• detecting, based on the performance, an instance of a cache utilization condition wherein a utilization metric is above a threshold level;
• and
• based on the cache utilization condition, adding the second cache to a pool of one or more caches which are to be available to receive micro-operations.

A system comprising:

• a memory;
• a processor coupled to the memory, wherein a core of the processor comprises:
• multiple caches comprising a first cache and a second cache, wherein the first cache is coupled to receive micro-operations from an instruction decoder, and wherein the second cache is coupled to receive data, or to receive instructions to be provided to the instruction decoder;
• first circuitry to monitor a performance of the multiple caches of the processor;
• second circuitry coupled to the first circuitry, the second circuitry to detect, based on the performance, an instance of a cache utilization condition wherein a utilization metric is above a threshold level;
• and
• third circuitry coupled to the second circuitry, wherein, based on the cache utilization condition, the third circuitry is to add the second cache to a pool of one or more caches which are to be available to receive micro-operations;
• and
• a display device coupled to the processor and the memory, the display device to display an image based on an execution of a program with the processor core.