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US 2023/0418756 A1Published application
Cache bypass
AssigneeMicron Technology, Inc.
InventorsEmanuele Confalonieri, Patrick Estep, Stephen S. Pawlowski, Nicola Del Gatto
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Abstract
Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.
Claims20
An apparatus, comprising:
- a memory device;
- and
- a memory controller coupled to the memory device, wherein the memory controller comprises a cache including a cache sequence controller configured to:
- determine a quantity of a given type of result of cache look-up operations associated with the cache;
- determine the quantity satisfies a bypass threshold;
- and
- cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.
4 more elements
A system, comprising:
- a memory device;
- and
- a memory controller coupled to the memory device and configured to perform cache look-up operations associated with a cache responsive to host read requests associated with the memory device, wherein the cache comprises:
- a metric logic including counters, the metric logic configured to collect, within a threshold amount of time, metrics related to the cache look-up operations;
- and
- a cache sequence controller to:
- determine, based on the collected metrics, quantity of a given type of result of the cache look-up operations associated with the cache;
- determine the quantity of the given type of result satisfies a bypass threshold;
- responsive to the determination that the quantity of the given type of result satisfies a bypass threshold:
- perform a cache look-up operation to determine a cache hit or a cache miss corresponding to a host read request;
- and
- in parallel with performance of the cache look-up operation, initiate a bypass read operation to read data corresponding to the host read request from the memory device.
9 more elements
A method, comprising:
- receiving a read request at a controller coupled to a memory device;
- performing cache look-up operations on a cache of a central controller portion;
- collecting, over a threshold amount of time, metrics associated with performing the cache look-up operations;
- determining, based on the collected metrics, a quantity of cache misses resulting from performance of a quantity of consecutive cache look-up operations associated with the cache;
- determining the quantity of cache misses satisfies a bypass threshold;
- and
- responsive to determining the quantity of cache misses satisfies the bypass threshold:
- causing performance of a bypass read operation that bypasses the cache and accesses the memory device in response to a host access request;
- and
- causing performance of a cache look-up operation associated with the cache in response to the host access request substantially contemporaneously with the performance of the bypass read operation.
7 more elements
Dependencies are inferred from the claim text.