Method for effectively increasing a memory on an fpga

A computer-implemented method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on an FPGA for effectively increasing a first memory of the FPGA, the method comprising:

• setting up an application on the FPGA, the application comprising a state interface, so that a current state of the application is read out from an outside at runtime;
• specifying, in the application, data which require a fast access at runtime, the data being marked as caching data, the caching data being preloaded at runtime;
• setting up a memory interface for reading out the first memory by the application, the bit width of the memory interface being model-adaptively specified such that the application is able to read out within one clock pulse all data stored in the first memory or a data structure stored in the first memory, which comprises a plurality of data entries;
• storing the specified caching data at least partially in a second memory during the setup of the application on the FPGA;
• storing a routine for managing the cache memory on the FPGA, the routine setting up the first memory as a cache memory for the specified data, the routine comprising a state input, which is linked with the state interface of the application;
• storing an overview on the FPGA, in which possible states of the application are assigned to data from the second memory which will probably be accessed by the application in a subsequent state, the routine continuously consulting the overview at runtime and transferring caching data which will probably be accessed by the application in a subsequent state from the second memory to the first memory;
• and
• accessing the caching data shifted to the first memory by the application, the access taking place via the memory interface.