Hardware-efficient pam-3 encoder and decoder
AssigneeNVIDIA Corporation
InventorsGautam Bhatia, Sunil Sudhakaran, Kyutaeg Oh
Life of this patent
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Abstract
A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.
Claims27
A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
- communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and at least one error correction channel;
- an encoder configured to:
- apply 11b7s encoding to a first plurality of the data bits to generate first PAM-3 symbols on some or all of the communication channels;
- and
- apply 3b2s encoding to a second plurality of the data bits to generate second PAM-3 symbols on at least some of the communication channels.
A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
- communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and at least one error correction channel;
- a decoder configured to:
- apply 11b7s decoding recover a first plurality of the data bits from first PAM-3 symbols on some or all of the communication channels;
- and
- apply 3b2s decoding to recover a second plurality of the data bits from PAM-3 symbols on at least some of the communication channels.
A method of communicating a burst of data bits over a serial data bus comprising a plurality of data channels, a plurality of auxiliary data channels, and at least one error correction channel, the method comprising:
- applying 11b7s encoding to a first plurality of the data bits to generate first PAM-3 symbols on the serial data bus;
- and
- apply 3b2s encoding to a second plurality of the data bits to generate second PAM-3 symbols on the serial data bus.
A system comprising:
- a machine memory;
- a data processor;
- a memory bus coupling the machine memory to the data processor, the memory bus comprising eight data channels, two auxiliary data channels, and one error correction channel;
- and
- an encoder configured to:
- apply 11b7s encoding to a first plurality of the data bits to generate first PAM-3 symbols on some or all of the communication channels;
- and
- apply 3b2s encoding to a second plurality of the data bits to generate second PAM-3 symbols on at least some of the communication channels.
Dependencies are inferred from the claim text.