US 2023/0418664 A1 · ADAPTIVE THREAD MANAGEMENT FOR HETEROGENOUS COMPUTING ARCHITECTURES

Abstract

An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture. A computing system includes multiple cores with at least two cores being capable of executing instructions of a same instruction set architecture (ISA), and therefore, are architecturally compatible. In an implementation, each of the at least two cores is a general-purpose central processing unit (CPU) core capable of executing instructions of a same ISA. However, the throughput and the power consumption greatly differ between the at least two cores based on their hardware designs. An operating system scheduler assigns a thread to a first core, and the first core measures thread dynamic behavior of the thread over a time interval. Based on the thread dynamic behavior, the scheduler reassigns the thread to a second core different from the first core.

Claims20

Dependent claims

An apparatus comprising:

a scheduler configured to:
receive an indication of thread dynamic behavior of a given thread assigned to a first core of a plurality of cores;
and
reassign the given thread to a second core different from the first core of the plurality of cores based at least in part on the indication of thread dynamic behavior of the given thread.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/846,593Filed 22 Jun 2022

Published

28 Dec 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 9/4881
By program, e.g. task dispatcher, supervisor, operating system: scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
G06F 9/30079
To perform miscellaneous control operations, e.g. NOP: pipeline control instructions, e.g. multicycle NOP
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/4893
Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues: taking into account power or heat criteria

Adaptive thread management for heterogenous computing architectures

Life of this patent

Adaptive thread management for heterogenous computing architectures

Life of this patent

Abstract

Claims20