Processor, operation method, and load-store device for implementation of accessing vector strided memory
AssigneeAndes Technology Corporation
InventorChia-Wei Hsu
Life of this patent
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Abstract
A processor, an operation method, and a load-store device are provided. The processor is adapted to access a memory. The processor includes a vector register file (VRF) and the load-store device. The load-store device is coupled to the VRF. The load-store device performs a strided operation on the memory. In a current iteration of the strided operation, the load-store device reads a plurality of first data elements at a plurality of discrete addresses in the memory and writes the first data elements into the VRF, or the load-store device reads a plurality of second data elements from the VRF and writes the second data elements into a plurality of discrete addresses in the memory during the current iteration of the strided operation.
Claims33
A processor, adapted to access a memory and comprising:
- a vector register file;
- and
- a load-store device, coupled to the vector register file and configured to perform a strided operation on the memory, wherein the load-store device reads a plurality of first data elements at a plurality of discrete addresses in the memory and writes the first data elements into the vector register file in a current iteration of the strided operation, or the load-store device reads a plurality of second data elements from the vector register file and respectively writes the second data elements into a plurality of discrete addresses in the memory in the current iteration of the strided operation.
An operating method of a processor, comprising:
- performing a strided operation on a memory by a load-store device;
- and
- in a current iteration of the strided operation, reading a plurality of first data elements at a plurality of discrete addresses in the memory by the load-store device and writing the first data elements into a vector register file, or reading a plurality of second data elements from the vector register file by the load-store device and respectively writing the second data elements into a plurality of discrete addresses in the memory.
A load-store device, comprising:
- a strided address generator, generating a plurality of strided addresses based on a current base address and a stride;
- and
- a load-store circuit, coupled to the strided address generator to receive the strided addresses, wherein the load-store circuit reads a plurality of first data elements in a memory based on the current base address and the strided addresses and writes the first data elements into a vector register file, or the load-store circuit reads a plurality of second data elements from the vector register file and respectively writes the second data elements into the memory based on the current base address and the strided addresses.
Dependencies are inferred from the claim text.