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US 2023/0418604 A1Published application
Reconfigurable vector processing in a memory
AssigneeIntel Corporation
InventorsAbhishek Anil Sharma, Pushkar Ranade, Wilfred Gomes, Sagar Suthram
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Abstract
In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a die comprising a memory, the die comprising:
- one or more memory layers having a plurality of banks to store data;
- and
- at least one complementary metal oxide semiconductor (CMOS) layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to one or more banks of the plurality of banks.
1 more element
A method comprising:
- receiving, in a memory, configuration information for a reconfigurable vector processor of the memory;
- storing the configuration information in a first array of the memory;
- and
- configuring the reconfigurable vector processor based at least in part on the configuration information.
1 more element
A system comprising:
- a processor comprising at least one core to execute instructions;
- and
- a memory coupled to the processor, the memory comprising:
- a first memory bank to store configuration information;
- a second memory bank to store first vector data;
- a third memory bank to store second vector data;
- and
- a reconfigurable vector processor to perform a vector computation on the first vector data and the second vector data, and provide result vector data to at least one of the second memory bank and the third memory bank, the reconfigurable vector processor comprising:
- a first functional unit to perform a first vector operation using at least one of the first vector data or the second vector data;
- and
- a second functional unit to perform another vector operation, wherein:
- in a first configuration, the second functional unit is coupled to the first functional unit;
- and
- in a second configuration, the second functional unit is independent of the first functional unit.
11 more elements
Dependencies are inferred from the claim text.