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AssigneeWestern Digital Technologies, Inc.
InventorsDaniel Joseph Linnen, Ramanathan Muthiah, Kirubakaran Periyannan
Estimating the term…
Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described herein are linear procedures that do not require logic branches. In one example, the MAC operation uses a set of linear MAC stages, wherein each linear stage processes MAC operations corresponding to one bit of a first multi-bit multiplicand being multiplied against a second multi-bit multiplicand. Examples are provided wherein the MAC procedures are performed as part of a neural network feedforward procedure where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.
A device, comprising:
A method for use with a device comprising a non-volatile memory (NVM) array formed on a die, the method comprising:
A device, comprising:
An apparatus for use with a device comprising a non-volatile memory (NVM) array formed on a die, the apparatus comprising:
Dependencies are inferred from the claim text.