Channel sizing for inter-kernel communication

A system, comprising:

• an integrated circuit;
• memory storing instructions;
• and
• a processor to execute the instructions to:
• implement a compiler;
• access, via the compiler, a high level program comprising instructions to implement a design on the integrated circuit;
• convert, via the compiler, the high level program into a low level program to be implemented on the integrated circuit;
• identify, via the compiler, a first kernel, a second kernel, and an inter-kernel channel based on the low level program or based on the high level program, wherein the first kernel writes data to the inter-kernel channel and the second kernel reads the data from the inter-kernel channel;
• identify, via the compiler, a potential stall due to expected writes to the inter-kernel channel by the first kernel, expected reads from the inter-kernel channel by the second kernel, or both,
• wherein the expected writes of the inter-kernel channel comprises, during a first cycle, the first kernel writing to the inter-kernel channel, and, during a second cycle, the first kernel not writing to the inter-kernel channel, and
• wherein the expected reads of the inter-kernel channel comprises, during a third cycle, the second kernel reading from the inter-kernel channel, and, during a fourth cycle, the second kernel not reading from the inter-kernel channel;
• modify, via the compiler, a size of the inter-kernel channel, based on a determination of a number of elements to be held in the inter-kernel channel to prevent the expected stall when the first kernel writes more elements to the inter-kernel channel than the second kernel reads or the second kernel reads more elements from the inter-kernel channel than the first kernel writes,
• wherein the size is based on the expected writes of the inter-kernel channel, the expected reads of the inter-kernel channel, or both;
• and
• provide, via the compiler, one or more kernels and the inter-kernel channel corresponding to the low level program for implementation on the integrated circuit, wherein the one or more kernels comprise the first kernel and the second kernel.