Computation circuit used in DCT, DST, IDCT and IDST

A computation circuit for discrete transformation comprising:

• a first term computation circuit and a second term computation circuit each comprising:
• a plurality of higher-bit computation circuits each configured to:
• selectively perform left-shift of different numbers of bits on a multiplicand according to a shift control signal determined according to a multiplier to generate a shifted multiplicand;
• output the shifted multiplicand according to an effective level of a bit effective control signal determined according to the multiplier;
• determine a sign of the shifted multiplicand according to a bit sign control signal determined by the multiplier;
• and
• perform left-shift of more number of bits on the shifted multiplicand when one of the higher-bit computation circuits corresponds to a higher bit without performing 2's complement computation thereon to generate a higher-bit computation result;
• a lowest bit computation circuit configured to output the multiplicand according to the effective level of a lowest bit effective control signal determined according to the multiplier, and determine the sign of the multiplicand according to a lowest bit sign control signal determined by the multiplier to generate a lowest bit computation result;
• and
• a first adder configured to add the higher-bit computation result and the lowest bit computation result to generate a term computation result;
• a third term computation circuit configured to output an addend according to the effective level of a term effective control signal, determine the sign of the added according to a term sign control signal and add the signed addend with a 2's complement sum to generate a third term computation result;
• a 2's complement computation circuit configured to perform a predetermine logic operation on the bit sign control signal of each of bits of the first term computation circuit and the second term computation circuit and the lowest bit sign control signal to generate the 2's complement sum;
• and
• a second adder configured to add the term computation result of each of the first term computation circuit and the second term computation circuit and the third term computation result to generate a total computation result.