Analog persistent circuit for storage access monitoring
AssigneeInternational Business Machines Corporation
InventorsKrishna Thangaraj, Heng Wu, Eric Raymond Evarts
Life of this patent
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Abstract
A memory system for storage access monitoring is provided. The memory system includes a media controller of a memory. An analog persistent circuit is coupled to the media controller and configured to monitor access to the memory. The analog persistent circuit stores persistent data related to memory access counts access signals from the command/address bus. A command/address bus is coupled to the analog persistent circuit. A memory array is communicatively coupled to the command address and the media controller.
Claims20
A memory system, comprising:
- a media controller of a memory;
- an analog persistent circuit coupled to the media controller, the analog persistent circuit configured to monitor access to the memory;
- a command address bus coupled to the analog persistent circuit;
- and
- a memory array communicatively coupled to the command address bus and the media controller.
A computer implemented method, comprising:
- monitoring, by an analog persistent circuit, a command address bus coupled to a memory array;
- identifying, by the analog persistent circuit, access instances to the memory array based on the monitoring of the command address bus;
- updating, by the analog persistent circuit, analog weights based on the access instances;
- determining, by a media controller, that the analog weights exceed a weights threshold;
- and
- selecting, by the media controller, a mitigation operation to perform on the memory array based on the access instances.
An analog persistent memory circuit, comprising:
- an input buffer configured to receive access signals from a command/address bus;
- a command component coupled to the input buffer, the command component configured to process access signals from the command/address bus;
- a logic component coupled to the command component, the logic component configured to process the access signals into one or more access counts;
- a memory component coupled to the command component and the logic component;
- the memory component configured to store access counts;
- and
- an output buffer coupled to the logic component, the output buffer configured to pass access count data to a memory controller.
Dependencies are inferred from the claim text.