Back to results
US 2023/0418503 A1Published application
Apparatuses and methods for memory alignment
AssigneeMicron Technology, Inc.
InventorJohn D. Leidel
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.
Claims21
-20. (canceled)
A method for memory alignment, comprising:
- receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements;
- and
- translating the logical address to a physical address for the data based on:
- a quantity of data bits of each of the plurality of byte-based memory elements;
- a quantity of padding bits of each of the plurality of byte-based memory elements;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address,
- wherein translating the logical address to the physical address comprises adjusting the logical address by a value equivalent to the quantity of padding bits multiplied by the quantity of byte-based memory elements from the start of the memory allocation to the logical address.
5 more elements
An apparatus, comprising:
- an array of memory cells configured to store a plurality of byte-based memory elements of a memory allocation;
- and
- a controller coupled to the array of memory cells and configured to cause:
- a logical address for data of a byte-based memory element of the memory allocation to be translated to a physical address for the data based on:
- a quantity of data bits of each of the plurality of byte-based memory elements;
- a quantity of padding bits of each of the plurality of byte-based memory elements;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- and
- the logical address to be adjusted by a value equivalent to the quantity of padding bits multiplied by the quantity of byte-based memory elements from the start of the memory allocation to the logical address.
7 more elements
A non-transitory machine-readable medium storing instructions executable by a processing resource to:
- receive, from a host, a logical address for data of a byte-based memory element of a memory allocation stored on a memory device;
- determine a physical address for the data based on:
- a quantity of data bits of the byte-based memory element;
- a quantity of padding bits of the byte-based memory element;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- store a plurality of byte-based memory elements of the memory allocation according to a byte-based alignment;
- and
- store the plurality of byte-based memory elements of the memory allocation according to a non-byte-based alignment,
- wherein the byte-based memory element is a first byte-based memory element of the memory allocation, and
- wherein in the non-byte-based alignment at least one data bit of the first byte-based memory element and at least one data bit of a second byte-based memory element of the memory allocation are logically adjacent at a location of the memory allocation other than a byte boundary and stored in physically adjacent memory cells of the array.
8 more elements
A method for memory alignment, comprising:
- receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements;
- translating the logical address to a physical address for the data based on:
- a quantity of data bits of each of the plurality of byte-based memory elements;
- a quantity of padding bits of each of the plurality of byte-based memory elements;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- performing a logical operation on the data at the physical address;
- padding the data with the quantity of padding bits after performing the logical operation;
- and
- sending the padded data to the host.
7 more elements
A method for memory alignment, comprising:
- receiving, from a host, a logical address for data of a byte-based memory element of a memory allocation including a plurality of byte-based memory elements;
- translating the logical address to a physical address for the data based on:
- a quantity of data bits of each of the plurality of byte-based memory elements;
- a quantity of padding bits of each of the plurality of byte-based memory elements;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- and
- storing, according to a non-byte-based alignment, logically adjacent bits in physically adjacent memory cells of the array, wherein the byte-based memory element is a first byte-based memory element of the memory allocation and the non-byte-based alignment includes:
- at least one padding bit of the first byte-based memory element logically adjacent to at least one padding bit of a second byte-based memory element of the memory allocation;
- and
- at least one data bit of the first byte-based memory element logically adjacent to at least one data bit of the second byte-based memory element at a location of the memory allocation other than a byte boundary.
8 more elements
An apparatus, comprising:
- an array of memory cells configured to store a plurality of byte-based memory elements of a memory allocation;
- a controller coupled to the array of memory cells and configured to cause a logical address for data of a byte-based memory element of the memory allocation to be translated to a physical address for the data based on:
- a quantity of data bits of each of the plurality of byte-based memory elements;
- a quantity of padding bits of each of the plurality of byte-based memory elements;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- wherein the controller is further configured to cause the data to be padded with the quantity of padding bits.
4 more elements
A system, comprising:
- a host;
- and
- a memory device coupled to the host and configured to:
- receive, from the host, a logical address for data of a byte-based memory element of a memory allocation stored on the memory device;
- determine a physical address for the data based on:
- a quantity of data bits of the byte-based memory element;
- a quantity of padding bits of the byte-based memory element;
- and
- a quantity of byte-based memory elements from a start of the memory allocation to the logical address;
- perform a logical operation on the data stored at the determined physical address;
- and
- subsequent to performing the logical operation, pad the data with the quantity of padding bits, wherein the host is configured to receive the padded data.
9 more elements
Dependencies are inferred from the claim text.