Method for programming an fpga

A method for programming an FPGA, wherein a library with elementary operations that are executable on the FPGA and a respective latency table for each of the elementary operations of the library are provided, wherein each latency table specifies, for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the respective operation, the latency of the respective operation during execution on the FPGA as a function of the input bit width of the respective operation and the clock rate of the FPGA, the method comprising:

• defining a data path that specifies a sequential execution on the FPGA of at least two elementary operations of the library;
• recording the latencies given by the respective input bit width of the respective elementary operations of the data path for a multiplicity of clock rates that are different from one another in the latency tables;
• adding the recorded latencies for every clock rate so that a total latency for the data path results in each case for this multiplicity of different clock rates;
• determining a lowest total latency;
• determining, for all clock rates, a ratio between a lowest total latency and a total latency at a respective clock rate;
• identifying a utilization of the FPGA for each clock rate;
• determining a lowest utilization of the FPGA;
• determining, for all clock rates, a ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate;
• and
• determining a quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA.