Semiconductor transistors having minimum gate-to-source voltage clamp circuits
AssigneeWolfspeed, Inc.
InventorsRahul R. Potera, Andreas Scholze, Jianwen Shao, Edward R. Van Brunt, Philipp Steinmann, James T. Richmond
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Abstract
Transistors are provided that comprise a silicon carbide based semiconductor layer structure, a first current terminal, a second current terminal, a gate terminal, and a minimum gate terminal-to-second current terminal voltage clamp circuit in the semiconductor layer structure that is coupled between the gate terminal and the second current terminal.
Claims39
A transistor, comprising:
- a silicon carbide based semiconductor layer structure;
- a first current terminal;
- a second current terminal;
- a gate terminal;
- and
- a minimum gate terminal-to-second current terminal voltage clamp circuit that is coupled between the gate terminal and the second current terminal.
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A transistor, comprising:
- a silicon carbide based semiconductor layer structure;
- a first current terminal;
- a second current terminal;
- a gate terminal;
- and
- a circuit comprising at least one diode that is coupled anode-to-cathode between the second current terminal and the gate terminal.
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A transistor, comprising:
- a silicon carbide based semiconductor layer structure;
- a first current terminal;
- a second current terminal that is electrically connected to a first source/drain contact;
- and
- a gate structure that includes a gate pad, a plurality of gate fingers, and one or more gate buses that electrically connect at least some of the gate fingers to the gate pad,
- where the semiconductor layer structure comprises:
- a drift region having a first conductivity type;
- a first well region having a second conductivity type in an upper portion of the drift region;
- a first implanted region in the first well region, the first implanted region having the first conductivity type and directly contacting the gate structure;
- and
- a second implanted region that has the second conductivity type;
- wherein the first and second implanted regions comprise a first diode that is interposed in between the first source/drain contact and the gate structure.
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Dependencies are inferred from the claim text.