Bias current with hybrid temperature profile

A hybrid circuit, comprising:

• a first current sink connected to:
• a zero temperature coefficient (ZTC) current source;
• corresponding gate terminals of a second transistor and a third transistor;
• and
• a ground terminal;
• a transistor connected to:
• a positive temperature coefficient (PTC) current source;
• a corresponding gate terminal of a first transistor;
• and
• the ground terminal;
• the first transistor connected to:
• a corresponding drain terminal of the second transistor;
• a corresponding drain terminal of the third transistor;
• a corresponding drain terminal of a fourth transistor;
• and
• the ground terminal;
• the second transistor connected to:
• the ZTC current source;
• the PTC current source;
• a corresponding gate terminal of the first current sink;
• a corresponding gate terminal of the transistor;
• the corresponding gate terminal of the first transistor;
• the corresponding gate terminal of the third transistor;
• and
• the ground terminal;
• the third transistor connected to:
• the ZTC current source;
• the corresponding gate terminal of the first current sink;
• the corresponding gate terminal of the second transistor;
• a corresponding drain terminal of the first transistor
• the corresponding drain terminal of the fourth transistor;
• and
• the ground terminal;
• the fourth transistor connected to:
• a voltage supply;
• a corresponding gate terminal of a current mirror;
• the corresponding drain terminal of the first transistor;
• and
• the corresponding drain terminal of the third transistor;
• the current mirror connected to the voltage supply.

A hybrid circuit, comprising:

• at least a first current source configured to source a first current having a first temperature slope;
• at least a second current source configured to source a second current having a second temperature slope different than the first temperature slope;
• and
• a circuit with fewer than seven transistors including:
• a first transistor configured to provide a third current having a third current magnitude of a higher of a zero current or a differential current between the second current and the first current,
• a second transistor configured to provide a fourth current having a fourth current magnitude identical to the third current magnitude, and
• a third transistor configured to provide a fifth current having a fifth current magnitude of a lesser of the first current or the second current, wherein a first sum of the fourth current magnitude and a first current magnitude of the first current equals to a hybrid current magnitude of a hybrid current.

A hybrid circuit, comprising:

• at least a first current sink configured to sink a first current having a first temperature slope;
• at least a second current sink configured to sink a second current having a second temperature slope different than the first temperature slope;
• and
• a circuit with fewer than six transistors including:
• a first transistor configured to provide a third current having a third current magnitude of a zero current or a differential current between the second current and the first current,
• a second transistor configured to provide a fourth current having a fourth current magnitude identical to the third current magnitude, and
• a third transistor configured to provide a fifth current having a fifth current magnitude of a lesser of the first current or the second current, wherein a first sum of the fourth current magnitude and a first current magnitude of the first current equals to a hybrid current magnitude of a hybrid current.

A hybrid circuit, comprising:

• a first current source coupled with:
• a zero temperature coefficient (ZTC) current source;
• corresponding gate terminals of a first transistor and a first current mirror;
• and
• a voltage supply;
• a second transistor coupled with:
• a positive temperature coefficient (PTC) current source;
• a corresponding gate terminal of a second current mirror and a corresponding source terminal of the first transistor;
• and
• the voltage supply;
• the second current mirror coupled with:
• a corresponding gate terminal of the second transistor;
• corresponding source terminals of the first transistor and the first current mirror;
• and
• the voltage supply;
• the first transistor coupled with:
• corresponding gate terminals of the first current source, the second transistor, the first current mirror, and the second current mirror;
• and
• the voltage supply;
• and
• the first current mirror coupled with:
• corresponding gate terminals of the first current source and the first transistor;
• and
• a corresponding source terminal of the second current mirror.