Time to digital converter arrangement with increased detection range

A method in a Time to Digital Converter, TDC, arrangement, the TDC arrangement comprising a first delay circuit, a set of phase detectors, a first multiplexer, a second delay circuit, a TDC, the method comprising:

• receiving, at the first delay circuit, a signal with multiple phases;
• outputting, from the first delay circuit, a delayed signal with corresponding multiple phases;
• comparing, by set of phase detectors, each phase of the multiple phases of the signal with a reference signal;
• receiving, at the first multiplexer, the delayed signal;
• outputting, from the first multiplexer, a selected one of the phases of the delayed signal in response to outputs from the set of phase detectors;
• receiving, at the second delay circuit, the reference signal;
• outputting, from the second delay circuit, a delayed reference signal;
• and
• detecting, by the TDC, a time difference between the delayed reference signal and the selected one of the phases of the delayed signal.

A device comprising a Phase Locked Loop, PLL circuit, the PLL circuit comprising:

• a first delay circuit configured to:
• receive a signal with multiple phases;
• and
• output a delayed signal with corresponding multiple phases;
• a set of phase detectors configured to:
• compare each phase of the multiple phases of the signal with a reference signal;
• a first multiplexer configured to:
• receive the delayed signal;
• and
• output a selected one of the phases of the delayed signal in response to outputs from the set of phase detectors;
• a second delay circuit configured to:
• receive the reference signal;
• and
• output a delayed reference signal;
• and
• a TDC configured to:
• detect a time difference between the delayed reference signal and the selected one of the phases of the delayed signal.