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US 2023/0417831 A1Published application
3d tap & scan port architectures
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
Claims14
A device comprising:
- a first surface including a test clock in contact point, a test mode select in contact point, a test reset in contact point, a first test data in contact point, and a first test data out contact point;
- a second surface opposite the first surface, the second surface including a test clock out contact point coupled with the test clock in contact point, a test mode select out contact point coupled with the test mode select in contact point, a test reset out contact point coupled with the test reset in contact point, a second test data out contact point coupled with the first test data in contact point, and a second test data in contact point;
- a Test Access Port (TAP) coupled to the test clock in contact point, the test mode select in contact point, the test reset in contact point, the first test data in contact point, and the second test data out contact point, wherein the TAP includes an instruction register;
- a reset-enable flip flop configurable in response to a signaling sequence of a test clock signal inputted to the test clock in contact point and a test mode select signal inputted to the test mode select in contact point, wherein the signaling sequence of the test clock signal and the test mode select signal to configure the reset-enable flip flop is different from a signaling sequence of the test clock signal and the test mode select signal to load an instruction to the instruction register in the TAP;
- an access-enable flip flop including a reset input coupled to the reset-enable flip flop and the test reset in contact point, wherein the access-enable flip flop includes an output, and wherein the access-enable flip flop can be reset only by the reset-enable flip flop or by a test reset signal inputted to the test reset in contact point;
- and
- a multiplexer including a first input coupled to the second test data in contact point, a second input coupled to the second test data out contact point, a control input coupled to the output of the access-enable flip flop, and an output coupled to the first test data out contact point.
4 more elements
A device comprising:
- a first surface including a test clock (TCK) input contact point, a test mode select (TMS) input contact point, a test data in (TDI) input contact point, a test reset (TRST) input contact point, and a test data out (TDO) output contact point;
- a second surface including a TCK output contact point, a TMS output contact point, a TDI output contact point, a TRST output contact point, and a TDO input contact point,
- a test access port (TAP) including a first input coupled to the TCK input contact point, a second input coupled to the TMS input contact point, a third input coupled to the TDI input contact point, a fourth input coupled to the TRST input contact point, a TDO output, a data output from a scan cell in a scan register within the TAP and a clock output from a state machine within the TAP,
- a register circuit including a data input coupled to the data output from the TAP, a clock input coupled to the clock output from the TAP, a reset input coupled to the TRST input contact point ad a data output, the register circuit including;
- a bit storage memory including a clock input coupled to the clock output from the TAP, a reset input coupled to the TRST input contact point, a data input, and a data output;
- and
- gating circuitry including a first input coupled to the data output from the TAP, a second input coupled to the data output of the bit storage memory, and a data output coupled to the data input of the bit storage memory;
- and
- a multiplexer including a first input coupled to the TDO output of the TAP, a second input coupled to the TDO input contact point, a data output coupled to the TDO output contact point, and a control input coupled to the data output of the bit storage memory.
6 more elements
Dependencies are inferred from the claim text.