# US 2023/0417830 A1 · In-line electrical detection of defects at wafer level > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0417830 A1 - Document ID: US20230417830A1 - Status: Published application - Kind: A1 - Application number: 17/851,261 - Filed: 2022-06-28 - Published: 2023-12-28 - Earliest claimed: 2022-06-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company - Inventors: Yu-Hsuan Huang; Chien-Liang Chen; Pei-Hsuan Lee - Web page: https://patentgrep.com/patent/US20230417830A1 ## CPC - G01R 31/307: of integrated circuits - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - G01N 23/2258: Measuring secondary ion emission, e.g. secondary ion mass spectrometry [SIMS] (mass-to-charge ratio analysis aspects of SIMS for material analysis G01N27/62) - G06T 7/0004: {Industrial image inspection} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01N 23/2251: using incident electron beams, e.g. scanning electron microscopy [SEM] - G01N 2223/611: patterned objects; electronic devices - G01N 2223/645: quality control - G06T 2207/30148: Semiconductor; IC; Wafer - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns. ## Claims ### Claim 1 A semiconductor manufacturing method, comprising: providing a plurality of patterns on a semiconductor substrate, wherein the patterns include an NMOS structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping arranged next to an N+/N well structure comprising at least one active structure formed with N-type doping in contact at least one source/drain structure of N-type doping; receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns. ### Claim 2 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the providing of the electron beam includes providing the electron beam with a landing energy effective to produce positive mode voltage contrast and the plurality of images includes at least one positive mode voltage contrast electron beam inspection (VC-EBI) image. ### Claim 3 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns further include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a P+/P well structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of P-type doping. ### Claim 4 (depends on 3) The semiconductor manufacturing method of claim 3 wherein the providing of the electron beam further includes providing the electron beam with a landing energy effective to produce negative mode voltage contrast and the plurality of images includes at least one negative mode voltage contrast electron beam inspection (VC-EBI) image. ### Claim 5 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns further include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to an NMOS structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping. ### Claim 6 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns further include an NMOS structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping arranged next to a second NMOS structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping. ### Claim 7 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns further include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a second PMOS structure comprising at least one active structure formed with N-type doping in contact at least one source/drain structure of P-type doping. ### Claim 8 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the providing of the plurality of patterns on the semiconductor substrate comprises performing front end-of-line (FEOL) processing of an integrated circuit (IC) manufacturing process, and the next process step comprises a back end-of-line (BEOL) processing step. ### Claim 9 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns are disposed on a surface of a substrate and the active structures of the patterns comprise mutually parallel linear fins each extending away from the surface of the substrate, and the patterns further include gate lines crossing and oriented perpendicular to the linear fins. ### Claim 10 (depends on 1) The semiconductor manufacturing method of claim 1 wherein the patterns are disposed on a wafer that also has an array of integrated circuit (IC) dies disposed thereon, and the patterns are disposed between the IC dies. ### Claim 11 A device comprising: a wafer; and patterns disposed on a surface of the wafer, wherein the patterns include at least one of: an NMOS structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping arranged next to an N*/N well structure comprising at least one active structure formed with N-type doping in contact at least one source/drain structure of N-type doping; and/or a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a P+/P well structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of P-type doping. ### Claim 12 (depends on 11) The device of claim 11 wherein the patterns include said NMOS structure arranged next to said N+/N well structure. ### Claim 13 (depends on 11) The device of claim 11 wherein the patterns include said PMOS structure arranged next to said P+/P well structure ### Claim 14 (depends on 11) The device of claim 11 wherein the patterns further include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to an NMOS structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping. ### Claim 15 (depends on 11) The device of claim 11 wherein the active structures of the patterns comprise one or more mutually parallel fins disposed on the surface of the wafer. ### Claim 16 (depends on 15) The device of claim 15 wherein the patterns further include gate lines crossing and oriented perpendicular to the fins. ### Claim 17 (depends on 11) The device of claim 11 further comprising: an array of integrated circuit (IC) dies disposed on the surface of the wafer, and the patterns are disposed on the surface of the wafer between the IC dies. ### Claim 18 A semiconductor manufacturing method, comprising: providing a plurality of patterns on a semiconductor substrate, wherein the patterns include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a P+/P well structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping; receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns. ### Claim 19 (depends on 18) The semiconductor manufacturing method of claim 18 wherein the providing of the electron beam further includes providing the electron beam with a landing energy effective to produce negative mode voltage contrast and the plurality of images includes at least one negative mode voltage contrast electron beam inspection (VC-EBI) image. ### Claim 20 (depends on 18) The semiconductor manufacturing method of claim 18 wherein the patterns further include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to an NMOS structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping.