US 2023/0417819 A1 · ENERGIZATION INSPECTION APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ENERGIZATION METHOD

Abstract

An electric connection inspection device includes: a cooling plate; an insulating plate provided on the cooling plate; a first measurement electrode provided on the insulating plate; and a second measurement electrode and a third measurement electrode provided above the first measurement electrode and located apart from the first measurement electrode. The insulating plate includes a variable thermal resistance mechanism. A semiconductor device can be installed between the first measurement electrode and the second measurement electrode and between the first measurement electrode and the third measurement electrode.

Claims28

Dependent claims

An energization inspection apparatus comprising:

a cooling plate;
an insulating plate provided on the cooling plate;
a first electrode provided on the insulating plate;
and
a second electrode and a third electrode provided above the first electrode and located away from the first electrode, wherein
the insulating plate includes a variable thermal resistance mechanism, and
a semiconductor device is allowed to be installed between the first electrode and the second electrode and between the first electrode and the third electrode.

4 more elements

A method for manufacturing a semiconductor device using an energization inspection apparatus including:

a cooling plate;
an insulating plate provided on the cooling plate and having a variable thermal resistance mechanism;
a first electrode provided on the insulating plate;
and
a second electrode and a third electrode provided above the first electrode and located away from the first electrode, the method comprising:
(a) preparing a semiconductor device including a drain electrode, a source electrode, and a gate pad electrode;
(b) after step (a), installing the semiconductor device between the first electrode and the second electrode and between the first electrode and the third electrode, electrically connecting the first electrode to the drain electrode, electrically connecting the second electrode to the source electrode, and electrically connecting the third electrode to the gate pad electrode;
(c) after step (b), adjusting a resistance value of the variable thermal resistance mechanism such that a maximum rated junction temperature of the semiconductor device is reached when a maximum rated forward current of the semiconductor device is applied to a built-in diode of the semiconductor device;
(d) after step (c), measuring a first on-voltage of the semiconductor device;
(e) after step (c), measuring a first leakage current when a specified voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode;
(f) after steps (d) and (e), applying a forward current to the built-in diode;
(g) after step (f), measuring a second on-voltage of the semiconductor device;
(h) after step (g) , calculating a value of change in voltage between the second on-voltage and the first on-voltage, and sorting the semiconductor device as a conforming product when the value of change in voltage is smaller than a specified value;
(i) after step (h), measuring a second leakage current when a specified voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode for the semiconductor device sorted as a conforming product;
and
(j) after step (i), calculating a value of change in current between the second leakage current and the first leakage current, and sorting the semiconductor device as a conforming product when the value of change in current is smaller than a specified value, wherein
step (a) includes:
(a1) preparing a semiconductor substrate of a first conductivity type that has a front surface and a back surface opposite to the front surface and is made of silicon carbide;
(a2) forming a semiconductor layer of the first conductivity type made of silicon carbide on the front surface of the semiconductor substrate;
(a3) forming a body region of a second conductivity type opposite to the first conductivity type in the semiconductor layer;
(a4) forming a source region of the first conductivity type in the body region;
(a5) forming a gate insulator film on the body region;
(a6) forming a gate electrode on the gate insulator film;
(a7) forming the source electrode on the body region and the source region such that the source electrode is electrically connected to the body region and the source region, and forming the gate pad electrode on the gate electrode such that the gate pad electrode is electrically connected to the gate electrode;
and
(a8) forming the drain electrode on the back surface of the semiconductor substrate, and
the built-in diode includes the body region and the semiconductor layer.

24 more elements

An energization method using an energization inspection apparatus including:

a cooling plate;
an insulating plate provided on the cooling plate and having a variable thermal resistance mechanism;
a first electrode provided on the insulating plate;
and
a second electrode and a third electrode provided above the first electrode and located away from the first electrode, the energization method comprising:
(a) preparing a semiconductor device including a drain electrode, a source electrode, and a gate pad electrode;
(b) after step (a), installing the semiconductor device between the first electrode and the second electrode and between the first electrode and the third electrode, electrically connecting the first electrode to the drain electrode, electrically connecting the second electrode to the source electrode, and electrically connecting the third electrode to the gate pad electrode;
(c) after step (b), adjusting a resistance value of the variable thermal resistance mechanism such that a maximum rated junction temperature of the semiconductor device is reached when a maximum rated forward current of the semiconductor device is applied to a built-in diode of the semiconductor device;
(d) after step (c), measuring a first on-voltage of the semiconductor device;
(e) after step (c), measuring a first leakage current when a specified voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode;
(f) after steps (d) and (e), applying a forward current to the built-in diode;
(g) after step (f), measuring a second on-voltage of the semiconductor device;
(h) after step (g) , calculating a value of change in voltage between the second on-voltage and the first on-voltage, and sorting the semiconductor device as a conforming product when the value of change in voltage is smaller than a specified value;
(i) after step (h), measuring a second leakage current when a specified voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode for the semiconductor device sorted as a conforming product;
and
(j) after step (i), calculating a value of change in current between the second leakage current and the first leakage current, and sorting the semiconductor device as a conforming product when the value of change in current is smaller than a specified value, wherein
the semiconductor device includes:
a semiconductor substrate of a first conductivity type that has a front surface and a back surface opposite to the front surface and is made of silicon carbide;
a semiconductor layer of the first conductivity type formed on the front surface of the semiconductor substrate and made of silicon carbide;
a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor layer;
a source region of the first conductivity type formed in the body region;
a gate insulator film formed on the body region;
a gate electrode formed on the gate insulator film;
the source electrode formed on the body region and the source region so as to be electrically connected to the body region and the source region;
the gate pad electrode formed on the gate electrode so as to be electrically connected to the gate electrode;
and
the drain electrode formed on the back surface of the semiconductor substrate, and
the built-in diode includes the body region and the semiconductor layer.

25 more elements

A method for manufacturing a semiconductor device, the method comprising:

(a) preparing a semiconductor device including a drain electrode, a source electrode, a gate pad electrode, and a built-in diode;
(b) after step (a), measuring a first on-voltage of the semiconductor device;
(c) after step (b), applying a forward current to the built-in diode;
(d) after step (c), measuring a second on-voltage of the semiconductor device;
(e) after step (d), calculating a value of change in voltage between the second on-voltage and the first on-voltage, and sorting the semiconductor device as a conforming product when the value of change in voltage is smaller than a first specified value;
(f) after step (e), measuring a leakage current when a predetermined voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode for the semiconductor device sorted as a conforming product;
and
(g) after step (f), sorting the semiconductor device as a conforming product when the leakage current is smaller than a second specified value.

5 more elements

A method for manufacturing a semiconductor device, the method comprising:

(a) preparing a semiconductor device including a drain electrode, a source electrode, a gate pad electrode, and a built-in diode;
(b) after step (a), measuring a first on-voltage of the semiconductor device;
(c) after step (a), measuring a first leakage current when a specified voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode;
(d) after steps (b) and (c), applying a forward current to the built-in diode;
(e) after step (d), measuring a second on-voltage of the semiconductor device;
(f) after step (e), calculating a value of change in voltage between the second on-voltage and the first on-voltage, and sorting the semiconductor device as a conforming product when the value of change in voltage is smaller than a first specified value;
(g) after step (f), measuring a second leakage current when a predetermined voltage is applied between the source electrode and the drain electrode in a state where the source electrode and the gate pad electrode are electrically short-circuited or in a state where a negative bias is applied to the gate pad electrode with respect to the source electrode for the semiconductor device sorted as a conforming product;
and
(h) after step (g), calculating a value of change in current between the second leakage current and the first leakage current, and sorting the semiconductor device as a conforming product when the value of change in current is smaller than a third specified value.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/255,145Filed 24 Feb 2022

Priority

JP 2021-05004124 Mar 2021

Published

28 Dec 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G01R 31/2621
Circuits therefor: for testing field effect transistors, i.e. FET's
G01R 31/2648
Testing of individual semiconductor devices: characterising semiconductor materials
G01R 31/01
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by…
G01R 31/54
Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections: testing…

Energization inspection apparatus, method for manufacturing semiconductor device, and energization method

Life of this patent

Energization inspection apparatus, method for manufacturing semiconductor device, and energization method

Life of this patent

Abstract

Claims28