Resistive random access memory structure and fabrication method thereof
AssigneeUnited Microelectronics Corp.
InventorsWen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
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Abstract
A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
Claims20
A resistive random access memory structure, comprising:
- a first inter-layer dielectric layer;
- a bottom electrode disposed in the first inter-layer dielectric layer;
- a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer;
- a through hole disposed in the capping layer, wherein the through hole partially exposes a top surface of the bottom electrode;
- a variable resistance layer disposed within the through hole;
- a top electrode disposed within the through hole and on the variable resistance layer;
- and
- a second inter-layer dielectric layer covering the top electrode and the capping layer.
A method of fabricating a resistive random access memory structure, comprising:
- forming a first inter-layer dielectric layer;
- forming a bottom electrode in the first inter-layer dielectric layer;
- forming a capping layer on the bottom electrode and on the first inter-layer dielectric layer;
- forming a through hole in the capping layer, wherein the through hole partially exposes a top surface of the bottom electrode;
- forming a variable resistance layer within the through hole;
- forming a top electrode within the through hole and on the variable resistance layer;
- and
- forming a second inter-layer dielectric layer covering the top electrode and the capping layer.
Dependencies are inferred from the claim text.