Diffusion barrier layer in programmable metallization cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAlbert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
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Abstract
Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.
Claims21
1-20. (canceled)
An integrated chip, comprising:
- a first conductive structure overlying a substrate;
- a data storage layer disposed on the first conductive structure;
- a second conductive structure overlying the data storage layer;
- and
- a first diffusion barrier layer disposed between the data storage layer and the second conductive structure, wherein a first diffusion activation temperature of the first diffusion barrier layer is different from a second diffusion activation temperature of the second conductive structure.
An integrated chip, comprising:
- a lower conductive structure overlying a substrate;
- and
- a memory cell overlying the lower conductive structure, wherein the memory cell comprises a dielectric layer, a first electrode over the dielectric layer, and a first diffusion barrier layer and a metal layer between the dielectric layer and the first electrode, wherein the first electrode comprises a diffusive species, wherein conductive materials of the first diffusion barrier layer and the metal layer are different from the diffusive species.
A method for forming an integrated chip, comprising:
- forming a data storage layer over a substrate;
- forming a diffusion barrier layer over the data storage layer;
- forming a top electrode over the diffusion barrier layer;
- and
- performing a heating process on the data storage layer, the diffusion barrier layer, and the top electrode, wherein a high temperature of the heating process is less than a diffusion activation temperature of the diffusion barrier layer.
Dependencies are inferred from the claim text.