Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Jun KOYAMA, Kiyoshi KATO
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Abstract
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
Claims16
(canceled)
A memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix;
- a first driver circuit electrically connected to a bit line;
- and
- a second driver circuit electrically connected to a word line,
- wherein each of the plurality of memory cells comprises a transistor and a capacitor,
- wherein one of a source and a drain of the transistor is electrically connected to the bit line,
- wherein the other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor,
- wherein a gate electrode of the transistor is electrically connected to the word line,
- wherein the transistor comprises a channel formation region in an oxide semiconductor layer,
- wherein the oxide semiconductor layer comprises a crystal,
- wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer,
- wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor, and
- wherein the potential of the gate electrode of the second transistor is held by turning off the first transistor.
A memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix;
- a first driver circuit electrically connected to a bit line;
- and
- a second driver circuit electrically connected to a word line,
- wherein each of the plurality of memory cells comprises a transistor and a capacitor,
- wherein one of a source and a drain of the transistor is electrically connected to the bit line,
- wherein the other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor,
- wherein a gate electrode of the transistor is electrically connected to the word line,
- wherein the transistor comprises a channel formation region in an oxide semiconductor layer,
- wherein the oxide semiconductor layer comprises a crystal,
- wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer,
- wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor,
- wherein the potential of the gate electrode of the second transistor is held by turning off the first transistor,
- wherein the oxide semiconductor layer comprises a layer comprising indium, and
- wherein, in the crystal, the layer comprising indium is parallel to the a-axis and a b-axis.
Dependencies are inferred from the claim text.