Semiconductor package and method of manufacturing the semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorKeunho CHOI
Life of this patent
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Abstract
A semiconductor package includes a package substrate, a chip stack structure on the package substrate, the chip stack structure including a base chip having a first thickness and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness, and a sealing member on an upper surface of the package substrate and on the chip stack structure. At least one of the plurality of upper chips includes a chip substrate having opposite first and second surfaces, a circuit layer on the first surface, and a stress compensation layer on the second surface and having an internal stress that offsets a warpage of the chip substrate.
Claims20
A semiconductor package, comprising:
- a package substrate;
- a chip stack structure on the package substrate, the chip stack structure comprising a base chip having a first thickness, and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness;
- and
- a sealing member on an upper surface of the package substrate and on the chip stack structure;
- wherein at least one of the plurality of upper chips comprises:
- a chip substrate having opposite first and second surfaces;
- a circuit layer on the first surface;
- and
- a stress compensation layer on the second surface, wherein the stress compensation layer has an internal stress that offsets a warpage of the chip substrate.
A semiconductor package, comprising:
- a package substrate;
- a semiconductor chip on an upper surface of the package substrate;
- a support spacer on the upper surface of the package substrate and spaced apart from the semiconductor chip;
- a chip stack structure on the semiconductor chip and the support spacer, the chip stack structure comprising a base chip having a first thickness and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness;
- and
- a sealing member on the upper surface of the package substrate, on the semiconductor chip, on the support spacer, and on the chip stack structure,
- wherein each of the plurality of upper chips comprises:
- a chip substrate having opposite first and second surfaces;
- a circuit layer on the first surface;
- and
- a stress compensation layer on the second surface and comprising an internal stress that offsets an internal stress of the chip substrate.
A method of manufacturing a semiconductor package, the method comprising:
- providing a first wafer having a first thickness;
- providing a second wafer having a second thickness less than the first thickness;
- dicing the first wafer to form a base chip;
- forming a stress compensation layer on a backside surface of the second wafer, the stress compensation layer comprising an internal stress selected to offset an internal stress within the second wafer;
- dicing the second wafer to form a plurality of upper chips;
- attaching the base chip to an upper surface of a package substrate;
- sequentially stacking the plurality of upper chips on the base chip;
- and
- forming a sealing member on the upper surface of the package substrate, on the base chip, and on the plurality of upper chips.
Dependencies are inferred from the claim text.