US 2023/0413575 A1 · 3D FERROELECTRIC MEMORY DEVICES

Abstract

A 3D FeRAM device includes a capacitor structure including a first capacitor electrode on a substrate, the first capacitor electrode extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a ferroelectric pattern surrounding a sidewall of the first capacitor electrode, and second capacitor electrodes surrounding and contacting an outer sidewall of the ferroelectric pattern, the second capacitor electrodes being spaced apart from each other in the vertical direction, an access transistor including a channel layer on the first capacitor electrode, a gate insulation layer surrounding an outer sidewall of the channel layer, and a gate electrode surrounding an outer sidewall of the gate insulation layer, a conductive pad on the channel layer, a contact plug on the conductive pad, and a bit line on the contact plug.

Claims20

Dependent claims

A 3D FeRAM device, comprising:

a capacitor structure including
a first capacitor electrode on a substrate, the first capacitor electrode extending in a vertical direction substantially perpendicular to an upper surface of the substrate,
a ferroelectric pattern surrounding a sidewall of the first capacitor electrode, and
second capacitor electrodes surrounding and contacting an outer sidewall of the ferroelectric pattern, the second capacitor electrodes being spaced apart from each other in the vertical direction;
an access transistor including
a channel layer on the first capacitor electrode,
a gate insulation layer surrounding an outer sidewall of the channel layer, and
a gate electrode surrounding an outer sidewall of the gate insulation layer;
a conductive pad on the channel layer;
a contact plug on the conductive pad;
and
a bit line on the contact plug.

9 more elements

A 3D FeRAM device, comprising:

first capacitor electrodes on a substrate, the first capacitor electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
a second capacitor electrode extending in the vertical direction through the first capacitor electrodes;
a ferroelectric pattern on a sidewall of the second capacitor electrode, the ferroelectric pattern contacting sidewalls of the first capacitor electrodes;
a gate electrode on an uppermost one of the first capacitor electrodes;
a channel layer extending through the gate electrode and contacting an upper surface of the second capacitor electrode, the channel layer having a cup shape;
a filling layer including a sidewall and a lower surface, the sidewall and the lower surface of the filling layer being covered by the channel layer;
a conductive pad contacting upper surfaces of the channel layer and the filling layer;
a gate insulation layer surrounding an outer sidewall of the channel layer and a sidewall of the conductive pad, the gate insulation layer contacting a sidewall of the gate electrode;
a contact plug on the conductive pad;
and
a bit line on the contact plug.

8 more elements

Dependencies are inferred from the claim text.

3d ferroelectric memory devices

Life of this patent

3d ferroelectric memory devices

Life of this patent

Abstract

Claims20