US 2023/0413567 A1Published application

Semiconductor memory device and method for manufacturing semiconductor memory device

AssigneeKioxia Corporation

InventorsHideto TAKEKIDA, Hisashi HARADA

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Abstract

A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.

Claims20

Dependent claims

A semiconductor memory device comprising:

a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one by one in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer being disposed on a first side in the first direction with respect to the first gate electrode layer, the second gate electrode layer having a length in a second direction intersecting the first direction that is shorter than that of the first gate electrode layer, the first gate electrode layer having a terrace portion that does not overlap with the second gate electrode layer in the first direction;
a first metal layer disposed at least on the first side with respect to the terrace portion of the first gate electrode layer;
and
a first columnar body disposed on the first side with respect to the terrace portion of the first gate electrode layer, wherein
the first columnar body including a conductive portion and an insulating portion, the conductive portion extending in the first direction, the conductive portion penetrating the first metal layer and connected to the terrace portion of the first gate electrode layer, the insulating portion disposed at least between the first metal layer and the conductive portion.

2 more elements

A method for manufacturing a semiconductor memory device, comprising:

forming a stacked body by alternately stacking a plurality of first layers and a plurality of second layers, the plurality of second layers different in material from the plurality of first layers, in a first direction;
forming a stepped portion in the stacked body, wherein in the stepped portion one layer and another layer in the plurality of first layers have different lengths in a second direction that intersects the first direction;
stacking an insulating third layer and a fourth layer, a material of the fourth layer being different from that of the third layer in at least the stepped portion in the order of the third layer and the fourth layer;
forming an insulator covering the stacked body and the fourth layer;
replacing the plurality of first layers with a plurality of gate electrode layers and replacing the fourth layer with a metal layer;
providing a hole extending in the first direction and penetrating the metal layer in the insulator;
and
forming a columnar body including a conductive portion penetrating the metal layer to be connected to a first gate electrode layer in the plurality of gate electrode layers, and an insulating portion disposed at least between the metal layer and the conductive portion, by utilizing the hole.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/176,176Filed 28 Feb 2023
Priority: JP 2022-09947121 Jun 2022
Published: 21 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND