Memory devices including different tier pitches, and related electronic systems

A NAND Flash memory device, comprising:

• a stack structure comprising:
• a first region including first tiers having a first tier pitch, at least some of the first tiers respectively comprising a conductive select gate structure and insulative material vertically adjacent the conductive select gate structure;
• an second region overlying the first region and including second tiers having a second tier pitch less than the first tier pitch, at least some of the second tiers respectively comprising a conductive word line structure and the insulative material vertically adjacent the conductive word line structure;
• and
• an third region overlying the second region and including third tiers having a third tier pitch less than the second tier pitch, at least some of the third tiers respectively comprising an additional conductive word line structure and the insulative material vertically adjacent the additional conductive word line structure;
• and
• strings of memory cells vertically extending through the stack structure.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a non-volatile memory device operably coupled to the processor device and comprising:
• a deck structure comprising:
• a first region including first tiers individually having a first vertical thickness, the first tiers respectively comprising conductive material and insulative material vertically adjacent the conductive material;
• an second region overlying the first region and including second tiers individually having a second vertical thickness less than the first vertical thickness, the second tiers respectively comprising the conductive material and the insulative material vertically adjacent the conductive material;
• and
• an third region overlying the second region and including third tiers individually having a third vertical thickness less than the second vertical thickness, the third tiers respectively comprising the conductive material and the insulative material vertically adjacent the conductive material;
• and
• strings of memory cells vertically extending through the deck structure and comprising:
• single level memory cells within the first region of the deck structure;
• triple level memory cells within the second region of the deck structure;
• and
• additional triple level memory cells within the third region of the deck structure.