Two transistor memory cells with source-drain coupling in one transistor

An integrated circuit (IC) device, comprising:

• a support structure;
• one or more elongated structures over the support structure;
• a first transistor having a channel region in a first portion of the one or more elongated structures;
• a second transistor having a channel region in a second portion of the one or more elongated structures;
• and
• an interconnect to connect a source region of the second transistor and a drain region of the second transistor,
• wherein:
• an angle between an edge of the support structure and a projection of an individual elongated structure of the one or more elongated structures is between about 10 degrees and 80 degrees, and
• a source region of the first transistor or a drain region of the first transistor is connected to at least one of the source region of the second transistor, the drain region of the second transistor, and a gate of the second transistor.

An integrated circuit (IC) device, comprising:

• a memory cell comprising a first transistor and a second transistor, wherein one of a source region of the first transistor and a drain region of the first transistor is connected to one of a source region of the second transistor, a drain region of the second transistor, or a gate of the second transistor, and wherein the source region of the second transistor is connected to the drain region of the second transistor;
• a first memory control line, connected to another one of the source region of the first transistor and the drain region of the first transistor;
• a second memory control line, connected to a gate of the first transistor;
• and
• a third memory control line, connected to:
• the gate of the second transistor when the one of the source region of the first transistor and the drain region of the first transistor is connected to the source region of the second transistor or the drain region of the second transistor, and
• the source region of the second transistor or the drain region of the second transistor when the one of the source region of the first transistor and the drain region of the first transistor is connected to the gate of the second transistor.