One-time programmable memory unit cell

A one-time programmable memory unit cell, comprising:

• a substrate comprising thereon a first active area and a second active area isolated from the first active area;
• a read select transistor disposed on the first active area, wherein the read select transistor comprises a first gate, a first gate dielectric layer between the first gate and the substrate, a first drain region in the substrate on one side of the first gate, and a first source region in the substrate on an opposing side of the first gate;
• a data storage transistor disposed on the first active area and serially connected to the read select transistor, wherein the data storage transistor comprises a second gate, a second gate dielectric layer between the second gate and the substrate, a second drain region in the substrate on one side of the second gate, a second source region in the substrate on an opposing side of the second gate, and a channel region between the second drain region and the second source region, wherein the second drain region merges with the first source region of the read select transistor, wherein the second gate comprises a main gate portion directly above the channel region, a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the data storage transistor, and wherein the second gate dielectric layer comprises a first portion between the drain region and the first extension gate portion, a second portion between the channel region and the main gate portion, and a third portion between the source region and the second extension gate portion, wherein the first portion and the third portion are thinner than the second portion;
• and
• a program select transistor disposed on the second active area, wherein the program select transistor comprises a third gate, a third gate dielectric layer between the third gate and the substrate, a third drain region in the substrate on one side of the third gate, and a third source region in the substrate on the other side of the third gate, wherein the third drain region is electrically coupled to the second gate of the data storage transistor.